1. Field of the Invention
Generally, the present invention relates to the fabrication of integrated circuits, and, more particularly, to the formation of metallization layers of reduced permittivity and packaging issues associated therewith.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits is currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable carriers for forming semiconductor devices, such as microprocessors, SRAMs ASICs (application specific ICs) and the like. The individual integrated circuits are arranged in an array form, wherein most of the manufacturing steps, which may involve up to 500 and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economical constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In the attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down and the peripheral chip areas are positioned as closely as possible to the substrate perimeter as it is compatible with substrate handling processes. Generally, most of the manufacturing processes are performed in an automated manner, wherein the substrate handling is performed at the back side of the substrate and/or the substrate edge.
Due to the ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper in combination with a low-K dielectric material has become a frequently used alternative in the formation of so-called interconnect structures comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer connections which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other is necessary to realize the connections between all internal circuit elements and I/O (input/output) power and ground pads of the circuit design under consideration. Hereby, the metal lines provide the electrical connections within a single metallization layer, whereas the vias are formed through the interlayer dielectric material to connect two metal lines of vertically adjacent metallization layers.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the field effect transistors but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to a reduced cross-sectional area. For this reason, traditional dielectrics such as silicon dioxide (k>3.6) and silicon nitride (k>5) are replaced by dielectric materials having a lower permittivity, which are therefore also referred to as low-k dielectrics having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the interconnect structure and any subsequent manufacturing processes of integrated circuits, production yield may be adversely affected by delamination of material residues, especially at the substrate edge where most of the substrate handling takes place, whereby delamination of such low-k layers, and thus substrate contamination, is substantially caused by the reduced mechanical stability of the low-k interconnect structure.
This situation may increase in subsequent manufacturing processes with the increasing introduction of flip-chip packaging techniques. As is generally acknowledged flip-chip packaging provides advantages in view of performance due to reduced lead lengths and I/O density, as substantially the whole chip area may be used for forming bumps that are to be connected with corresponding bumps or pads of a carrier or package substrate. During the process of attaching the package substrate to the chip including the low-k interconnect structure and a bump layer, a certain amount of pressure and/or heat is applied to the composite device to establish a reliable connection between each of the bumps of the chip and the bumps or pads of the package substrate. The heat and/or mechanical stress during the packaging may, however, affect the low-k interconnect structure.
In modern microprocessors, where a large number of I/O lines are required, up to several hundred or several thousand bumps are reliably to be connected with the corresponding bumps or pads of the package substrate. Hence, especially in microprocessors built with a low-k dielectric interconnect structure, the probability for cracking and delamination in the interconnect structure formed of the low-k dielectric of reduced mechanical strength is remarkably increased and a decrease of production yield may be observed, thereby partly off-setting the advantages obtained by increasing the substrate size and minimizing substrate edge regions. The problem is even exacerbated when the microprocessor chips are to be attached to organic package substrates, owing to the significant thermal mismatch between silicon and the organic material forming the package substrate. Moreover, even though under-fill materials are typically introduced into the space between the package substrate and the attached silicon chip to compensate a portion of the mechanical stress caused by the different coefficients of the thermal expansion, the reduced mechanical stability of inter-connect structures comprised of low-k dielectrics may even negatively affect the failure rate during the operation of the device.
With reference to FIGS. 1a and 1b, the problems involved in packaging a semiconductor device having an interconnect structure comprised of a low-k dielectric are discussed in more detail.
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 including an interconnect structure 110 formed of a low-k dielectric material for a device having, for example, a critical design dimension of 130 nm. The semiconductor device 100 comprises a substrate 101, which includes a large number of circuit elements, such as transistors, capacitors and the like, or which may include further metal line layers and intermediate via layers that are for convenience not shown in FIG. 1a. Instead, and representative of any of the above-mentioned circuit features, a contact portion 102 is illustrated and is connected to the above located interconnect structure 110. The interconnect structure 110 comprises a first metal line 111 and a first via 112 formed in a low-k dielectric layer 113. The metal line 111 may be comprised of copper and a conductive barrier layer, such as a tantalum/tantalum nitride layer located between the copper and the dielectric material 113. Similarly, the via 112 may be filled with copper and may be separated from the dielectric material 113 by a conductive barrier layer. For convenience, any details of the metal line 111 and the via 112 are not shown in FIG. 1a. A capping layer 114 is located between the dielectric layer 113 and the substrate 101. For example, the low-k dielectric layer 113 may be comprised of hydrogenated silicon oxycarbide (SiCOH) and the capping layer 114 may be comprised of nitrogen-enriched silicon carbide (SiCN). The interconnect structure 110 further comprises a second metal line 115 connected to a second via 116, which, in turn, is connected to the first metal line 111. The second metal line 115 and the second via 116 are formed in a second low-k dielectric layer 118, which, in turn, is separated from the first low-k dielectric layer 113 by a further capping layer 117. Regarding the material composition of the metal line 115, the via 116, the second low-k dielectric layer 118 and the capping layer 117, the same materials may be used as in the corresponding components of the underlying metallization layer. It should be appreciated that typically a plurality of first metal lines 111 is provided in the low-k dielectric layer 113, which may be connected by corresponding vias 112 to any lower lying regions or layers. The same holds true for the second metal lines 115 and the second vias 116 in the second low-k dielectric layer 118. Due to the relatively low permittivity of the layers 113 and 118, for instance 3 or less, the capacitance between neighboring first metal lines 111 and between neighboring second metal lines 115 is reduced compared to an interconnect structure 110 having formed therein dielectric layers 113, 118 comprised of silicon dioxide. The semiconductor device 100, when representing an advanced microprocessor of the 130 nm technology node, may include up to eight metal line layers which are connected to each other via corresponding intermediate via layers. Consequently, the interconnect structure 100 as shown in FIG. 1a exhibits a significantly reduced mechanical stability for the benefit of an increased operating speed.
FIG. 1b schematically shows the semiconductor device 100 with a bump layer 120 formed above the interconnect structure 110 and attached to the bump layer 120 is a package substrate 130. The package substrate 130 comprises a base portion 132, which may be comprised of an organic material in view of economic constraints, and may also include a plurality of bumps or contact pads 131, which match in position and size corresponding bumps 121 formed in the bump layer 120. Owing to a mismatch in the thermal expansion coefficient between the base portion 132 and the substrate 101, delamination and cracking 119 may occur in the interconnect structure 110 during and after attaching the package. substrate 130 to the bump layer 120, which may, however, lead to a significantly reduced production yield during the fabrication of the device 100 and to an increased failure rate during the operation of the packaged device 100.
A typical process flow for forming the semiconductor device 100 as shown in FIGS. 1a and 1b may comprise the following processes. After forming any circuit elements and any contact regions, such as the portion 102, in and on the substrate 101, the capping layer 114 may be formed followed by the formation of the dielectric layer 113, wherein, for instance, a plasma enhanced chemical vapor deposition (PECVD) process may be employed for SiCOH, whereas advanced spin-on techniques may be used for low-k polymer materials. Thereafter, trenches and corresponding via openings may be formed in the dielectric layer 113 by, for instance, well approved via-first-trench-last approaches based on established photolithography and etch techniques, wherein the capping layer 114 may serve as an etch stop layer for the etch process to form the via opening. However, depending on the critical design dimensions, other well-established regimes, such as a trench-first-via-last approach, may be employed. Thereafter, conductive barrier layers and possibly seed layers may be formed by appropriate techniques, such as sputter deposition, and finally the copper may be filled in by, for instance, electroplating, wherein any excess metal may be removed by chemical mechanical polishing. Thereafter, the capping layer 117 may be formed by substantially the same process sequence as described above to form the metal lines 115 and the vias 116 in the dielectric layer 118. After all of the metal line levels and via levels of the interconnect structure 110 are completed, the bump layer 120 may be formed by well-known techniques, such as sputter deposition of under-bump metallization layers followed by a lithography-assisted electroplating process for forming the bumps 121. As previously mentioned, the substrate handling during the formation of the interconnect structure 110 in combination with any CMP processes may result in the formation of cracking and delamination 119 owing to low-k material deposition at the substrate edge and the reduced mechanical stability of the interconnect structure during the CMP process. These yield-compromising factors, in combination with the main source for significant reduction of the yield, that is, the flip-chip bonding of the package substrate 130 to the bump layer 120, especially when organic base portions 132 are used, renders an economic production of sophisticated semiconductor devices including low-k interconnect structure difficult.
In view of the above-identified problems, there exists a need for an improved technique that enables the achievement of higher production yield during the packaging process while still maintaining high performance of advanced semiconductor devices using low-k dielectric materials.